Semiconductor device structure including forksheet transistors and methods of forming the same

ABSTRACT

A method for forming a semiconductor device structure includes forming first, second, and third fin structures from a substrate, wherein the first fin structure includes a first plurality of semiconductor layers, the second fin structure includes a second plurality of semiconductor layers, and the third fin structure includes a third plurality of semiconductor layers, and wherein each of the first, second, and third plurality of semiconductor layers comprises first semiconductor layers and second semiconductor layers. The method includes forming an insulating material between the first, second, and third fin structures, forming an end cut in the second fin structure, the end cut exposing an upper portion of the substrate, forming a dielectric fin in the end cut, forming a first dielectric feature on the insulating material and between the first fin structure and the dielectric fin, forming a second dielectric feature on the insulating material and between the dielectric fin structure and the third fin structure, forming a sacrificial gate stack on a portion of the first fin structure, the second fin structure, the third fin structure, the first dielectric feature, and the second dielectric feature, removing a portion of the first fin structure, the third fin structure, and the dielectric fin not covered by the sacrificial gate stack, removing the sacrificial gate stack to expose portions of the first, second, and third fin structures, removing the second semiconductor layers of the first, second, and third plurality of semiconductor layers, and forming a gate electrode layer to surround at least three surfaces of the first semiconductor layers of the first, second, and third plurality of semiconductor layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 17/225,859 filed on Apr. 8, 2021, which is incorporated byreference in its entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experiencedexponential growth. Technological advances in IC materials and designhave produced generations of ICs where each generation has smaller andmore complex circuits than the previous generation. In the course of ICevolution, functional density (i.e., the number of interconnecteddevices per chip area) has generally increased while geometry size(i.e., the smallest component (or line) that can be created using afabrication process) has decreased. This scaling down process generallyprovides benefits by increasing production efficiency and loweringassociated costs. Such scaling down presents new challenge. For example,transistors using nanowire channels have been proposed to achieveincreased device density, greater carrier mobility and drive current ina device. As device size reduces, there is a continuous need to improveprocessing and manufacturing ICs.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1-2 are perspective views of various stages of manufacturing asemiconductor device structure, in accordance with some embodiments.

FIGS. 3A-12A are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line A-A ofFIG. 3C, in accordance with some embodiments.

FIGS. 3B-12B are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line B-B ofFIG. 3C, in accordance with some embodiments.

FIGS. 3C-12C are top views of the semiconductor device structure of FIG.2 in accordance with some embodiments.

FIG. 13 is a perspective view of one of the various stages ofmanufacturing the semiconductor device structure, in accordance withsome embodiments.

FIGS. 14A-19A are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line A-A ofFIG. 14D and line A-A of FIG. 13 , in accordance with some embodiments.

FIGS. 14B-19B are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line B-B ofFIG. 14D, in accordance with some embodiments.

FIGS. 14C-19C are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line C-C ofFIG. 13 .

FIGS. 14D-19D are top views of the semiconductor device structure ofFIG. 13 , in accordance with some embodiments.

FIGS. 20-25 are cross-sectional views of various stages of manufacturingthe semiconductor device structure of FIG. 19A in accordance with someembodiments.

FIG. 26 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure of FIG. 19C, inaccordance with some embodiments.

FIG. 27 is a perspective view of one of various stages of manufacturingthe semiconductor device structure, in accordance with some embodiments.

FIG. 28 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure, in accordance withsome embodiments.

FIG. 29 is a perspective view of one of various stages of manufacturinga semiconductor device structure, in accordance with some embodiments.

FIGS. 30A-38A are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line A-A ofFIG. 30C, in accordance with some embodiments.

FIGS. 30B-38B are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line B-B ofFIG. 30C, in accordance with some embodiments.

FIGS. 30C-38C are top views of various stages of manufacturing thesemiconductor device structure of FIG. 29 , in accordance with someembodiments.

FIG. 39 is a perspective view of one of various stages of manufacturingthe semiconductor device structure, in accordance with some embodiments.

FIGS. 40A-45A are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line A-A ofFIG. 40D and line A-A of FIG. 39 , in accordance with some embodiments.

FIGS. 40B-45B are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line B-B ofFIG. 40D, in accordance with some embodiments.

FIGS. 40C-45C are cross-sectional side views of various stages ofmanufacturing the semiconductor device structure taken along line C-C ofFIG. 39 .

FIGS. 40D-45D are top views of the semiconductor device structure ofFIG. 39 in accordance with some embodiments.

FIGS. 46-48 are cross-sectional views of various stages of manufacturingthe semiconductor device structure of FIG. 45A in accordance with someembodiments.

FIG. 49 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure of FIG. 45C, inaccordance with some embodiments.

FIG. 50 is a perspective view of one of various stages of manufacturingthe semiconductor device structure, in accordance with some embodiments.

FIG. 51 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure, in accordance withsome embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “over,” “on,” “top,” “upper” and the like, may be used hereinfor ease of description to describe one element or feature'srelationship to another element(s) or feature(s) as illustrated in thefigures. The spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. The apparatus may be otherwiseoriented (rotated 90 degrees or at other orientations) and the spatiallyrelative descriptors used herein may likewise be interpretedaccordingly.

While the embodiments of this disclosure are discussed with respect tonanosheet channel FETs, implementations of some aspects of the presentdisclosure may be used in other processes and/or in other devices, suchas planar FETs, Fin-FETs, Horizontal Gate All Around (HGAA) FETs,Vertical Gate All Around (VGAA) FETs, and other suitable devices. Aperson having ordinary skill in the art will readily understand othermodifications that may be made are contemplated within the scope of thisdisclosure. In cases where gate all around (GAA) transistor structuresare adapted, the GAA transistor structures may be patterned by anysuitable method. For example, the structures may be patterned using oneor more photolithography processes, including double-patterning ormulti-patterning processes. Generally, double-patterning ormulti-patterning processes combine photolithography and self-alignedprocesses, allowing patterns to be created that have, for example,pitches smaller than what is otherwise obtainable using a single, directphotolithography process. For example, in one embodiment, a sacrificiallayer is formed over a substrate and patterned using a photolithographyprocess. Spacers are formed alongside the patterned sacrificial layerusing a self-aligned process. The sacrificial layer is then removed, andthe remaining spacers may then be used to pattern the GAA structure.

FIGS. 1-28 show exemplary sequential processes for manufacturing asemiconductor device structure 100, in accordance with some embodiments.It is understood that additional operations can be provided before,during, and after processes shown by FIGS. 1-28 , and some of theoperations described below can be replaced or eliminated, for additionalembodiments of the method. The order of the operations/processes may beinterchangeable.

FIG. 1 is a perspective view of one of various stages of manufacturingthe semiconductor device structure 100, in accordance with someembodiments. As shown in FIG. 1 , a semiconductor device structure 100includes a stack of semiconductor layers 104 formed over a front side ofa substrate 101. The substrate 101 may be a semiconductor substrate. Thesubstrate 101 may include a single crystalline semiconductor materialsuch as, but not limited to silicon (Si), germanium (Ge), silicongermanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb),gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminumarsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonyphosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indiumphosphide (InP). In this embodiment, the substrate 101 is made of Si. Insome embodiments, the substrate 101 is a silicon-on-insulator (all)substrate, which includes an insulating layer (not shown) disposedbetween two silicon layers. In one aspect, the insulating layer is anoxide.

The substrate 101 may include various regions that have been doped withimpurities (e.g., dopants having p-type or n-type conductivity).Depending on circuit design, the dopants may be, for example boron for ap-type (or p-channel) field effect transistor (FET) and phosphorus foran n-type (or n-channel) FET.

The stack of semiconductor layers 104 includes alternating semiconductorlayers made of different materials to facilitate formation of nanosheetchannels in a multi-gate device, such as nanosheet channel FETs orforksheet FETs. In some embodiments, the stack of semiconductor layers104 includes first semiconductor layers 106 (106 a-106 b) and secondsemiconductor layers 108 (108 a-108 b). In some embodiments, the stackof semiconductor layers 104 includes alternating first and secondsemiconductor layers 106, 108. The first semiconductor layers 106 arealigned with the second semiconductor layers 108. The firstsemiconductor layers 106 and the second semiconductor layers 108 aremade of semiconductor materials having different etch selectivity and/oroxidation rates. For example, the first semiconductor layers 106 may bemade of Si and the second semiconductor layers 108 may be made of SiGe.In some examples, the first semiconductor layers 106 may be made of SiGeand the second semiconductor layers 108 may be made of Si. In somecases, the SiGe in the first or second semiconductor layers 106, 108 canhave a germanium composition percentage between about 10% and about 80%.Alternatively, in some embodiments, either of the semiconductor layers106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP,InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or anycombinations thereof.

The first semiconductor layers 106 or portions thereof may formnanosheet channel(s) of the semiconductor device structure 100 in laterfabrication stages. The term nanosheet is used herein to designate anymaterial portion with nanoscale, or even microscale dimensions, andhaving an elongate shape, regardless of the cross-sectional shape ofthis portion. Thus, this term designates both circular and substantiallycircular cross-section elongate material portions, and beam orbar-shaped material portions including, for example, a cylindrical inshape or substantially rectangular cross-section. The nanosheetchannel(s) of the semiconductor device structure 100 may be surroundedby a gate electrode. For example, the nanosheet channel(s) of aforksheet transistor may have at least three surfaces surrounded by thegate electrode. The semiconductor device structure 100 may include ananosheet transistor and/or a forksheet transistor. The nanosheettransistors may be referred to as nanowire transistors, gate-all-around(GAA) transistors, multi-bridge channel (MBC) transistors, or anytransistors having the gate electrode surrounding the channels.

It is noted that while two layers of the first semiconductor layers 106and two layers of the second semiconductor layers 108 are alternatelyarranged as illustrated in FIG. 1 , it can be appreciated that anynumber of first and second semiconductor layers 106, 108 can be formedin the stack of semiconductor layers 104, depending on the predeterminednumber of channels for the semiconductor device structure 100. In someembodiments, the number of first semiconductor layers 106, which is thenumber of channels, is between 3 and 8.

The first and second semiconductor layers 106, 108 are formed by anysuitable deposition process, such as epitaxy. By way of example,epitaxial growth of the layers of the stack of semiconductor layers 104may be performed by a molecular beam epitaxy (MBE) process, ametalorganic chemical vapor deposition (MOCVD) process, and/or othersuitable epitaxial growth processes.

The substrate 101 may include a sacrificial layer 107 on the stack ofsemiconductor layers 104. The sacrificial layer 107 protects the stackof semiconductor layers 104 during the subsequent processes and isremoved along with a portion of a cladding layer (FIG. 12A) prior toformation of the sacrificial gate stack (FIG. 13 ). In cases where thefirst semiconductor layer 106 of the stack of semiconductor layers 104is Si, the sacrificial layer 107 includes SiGe epitaxially grown on thefirst semiconductor layer 106.

Each first semiconductor layer 106 may have a thickness in a rangebetween about nm and about 30 nm. Each second semiconductor layer 108may have a thickness that is equal, less, or greater than the thicknessof the first semiconductor layer 106. In some embodiments, each secondsemiconductor layer 108 has a thickness in a range between about 2 nmand about 50 nm. The second semiconductor layers 108 may eventually beremoved and serve to define a vertical distance between adjacentchannels for the semiconductor device structure 100. The sacrificiallayer 107 may have a thickness that is equal, less, or greater than thethickness of the first semiconductor layer 106. The thickness of thesacrificial layer 107 may range from about 2 nm to 50 nm. The thicknessof the first semiconductor layer 106, the second semiconductor layer108, and the sacrificial layer 107 may vary depending on the applicationand/or device performance considerations.

A mask structure 110 is formed over the sacrificial layer 107. The maskstructure 110 may include an oxygen-containing layer and anitrogen-containing layer. The oxygen-containing layer may be a padoxide layer, such as a SiO₂ layer. The nitrogen-containing layer may bea pad nitride layer, such as Si₃N₄. The mask structure 110 may be formedby any suitable deposition process, such as chemical vapor deposition(CVD) process.

FIG. 2 is a perspective view of one of the various stages ofmanufacturing the semiconductor device structure 100, in accordance withsome embodiments. Fin structures 112 (112 a-112 c) are formed from thestack of semiconductor layers 104. Each fin structure 112 has an upperportion including the semiconductor layers 106, 108 and a well portion116 formed from the substrate 101. The fin structures 112 may befabricated using multi-patterning operations including photo-lithographyand etching processes. The etching process can include dry etching, wetetching, reactive ion etching (RIE), and/or other suitable processes.The etching process forms trenches 114 (e.g., 114 a, 114 b, 114 c, 114d) in unprotected regions through the mask structure 110, through thestack of semiconductor layers 104, and into the substrate 101, therebyleaving the plurality of extending fin structures 112 (e.g., 112 a, 112b, 112 c). The trenches 114 extend along the X direction. The trenches114 may be etched using a dry etch (e.g., RIE), a wet etch, and/orcombination thereof.

As shown in FIG. 2 , the fin structure 112 a may have a first width W1,and the fin structures 112 b, 112 c may each has a second width W2. Thesecond width W2 may be equal, less, or greater than the first width W1.In one embodiment shown in FIG. 2 , the first width W1 is greater thanthe second width W2. The first and second widths W1, W2 may correspondto the device's channel width. In one embodiment, the second width W2 isin a range between 5 nm to about 120 nm, for example about 10 nm toabout 100 nm.

The distance between adjacent fin structures may be defined by thedistance between a first sidewall of one fin structure and a secondsidewall of the adjacent fin structure facing the first sidewall. Forexample, the fin structure 112 a and the fin structure 112 b areseparated by a first distance D1. The fin structure 112 b and the finstructure 112 c are separated by a second distance D2. The first andsecond distances D1, D2 may vary depending on the layouts of the finstructures in a SRAM cell. The width of the fin structures 112 a, 112 b,112 c may also vary depending on the channel width of the devices neededin the semiconductor device structure 100. The devices with a widerchannel, such as the device fabricated from the fin structures 112 a,112 b, may be more suitable for high-speed applications, such as a NANDdevice. The devices with a narrower channel, such as the devicefabricated from the fin structures 112 b, 112 c, may be more suitablefor low-power and low-leakage applications, such as an inverter device.Therefore, trenches with wider width (e.g., trench 114 a) may be formedin regions where devices/transistors require higher voltage currentand/or higher performance, while trenches with narrower width (e.g.,trench 114 b) may be formed in regions where greater density ofdevices/transistors is desired.

The first distance D1 and the second distance D2 define the width of thesubsequent first and second dielectric features 130, 134 (FIGS.12A-12C). In one embodiment shown in FIG. 2 , the first distance D1 isgreater than the second distance D2. The second distance D2 may be in arange from about 2 nm to about 40 nm, for example about 3 nm to about 30nm. With the smaller distance D2 (i.e., reduced fin-to-fin spacing)between the fin structures 112 b and 112 c, layers of a first dielectricfeature 130 (FIGS. 4A-4C) subsequently formed in the trench 114 b maymerge, while the trench 114 a between the fin structures 112 a and 112 bremains open after the deposition of layers of the first dielectricfeature 130 due to the wider distance D1. The merged layers of the firstdielectric feature 130 allow the nanosheet channels to attach to bothsides of the first dielectric feature 130 and form forksheet transistorsat a later stage. The reduced fin-to-fin spacing and fork-like nanosheettransistors enable greater device density (even with greater channelwidth) and superior area and performance scalability.

Depending on the layouts of the SRAM cell, the trenches 114 c and 114 dmay have a width corresponding to the first distance D1 or the seconddistance D2. In one embodiment shown in FIG. 2 , the trenches 114 c, 114d have a width corresponding to the first distance D1. In someembodiments, a fin structure (not shown) having a width corresponding toW1 may be disposed adjacent to and spaced apart the fin structure 112 aby the trench 114 d. Likewise, a fin structure (not shown) having awidth corresponding to W2 may be disposed adjacent to and spaced apartthe fin structure 112 c by the trench 114 c.

FIGS. 3C-12C are top views of the semiconductor device structure 100 ofFIG. 2 , which may represent a portion of the layout of active finstructures in a SRAM cell 103. For example, a 6T SRAM cell may includetwo pull-up (PU) transistors, two pass-gate (PG) transistors, and twopull-down (PD) transistors. In one embodiment shown in FIGS. 3C-12C, thefin structures 112 b and 112 c can be used to form PU transistors andthe fin structure 112 a can be used to form PD transistor or PGtransistor in the 6T SRAM cell. FIGS. 3A-12A are cross-sectional sideviews of various stages of manufacturing the semiconductor devicestructure 100 taken along line A-A of FIG. 3C, in accordance with someembodiments. FIGS. 3B-12B are cross-sectional side views of variousstages of manufacturing the semiconductor device structure 100 takenalong line B-B of FIG. 3C, in accordance with some embodiments.

In FIGS. 4A-4C, a first dielectric feature 130 is formed in the trench114 b (FIGS. 3A and 3B) between the fin structures 112 b and 112 c. Insome embodiments, the first dielectric feature 130 includes a firstdielectric layer 126, a second dielectric layer 128, and a thirddielectric layer 119. The first dielectric layer 126 is in contact withat least the stack of semiconductor layers 104 (e.g., firstsemiconductor layers 106 a-b and second semiconductor layers 108 a-b),the third dielectric layer 119 is formed over the first dielectric layer126, and the second dielectric layer 128 is formed between and incontact with the first dielectric layer 126 and the third dielectriclayer 119. In some embodiment, the first dielectric layer 126 may beomitted. That is, the second dielectric layer 128 is in contact with atleast the stack of semiconductor layers 104 (e.g., first semiconductorlayers 106 a-b and second semiconductor layers 108 a-b). The firstdielectric layer 126 and the third dielectric layer 119 may be formed ofthe same material. In some embodiments, the first and third dielectriclayers 126, 119 include an oxygen-containing dielectric material such asSiO₂. The second dielectric layer 128 may be a low-K dielectric material(e.g., a material having a K value lower than 7). In some embodiments,the second dielectric layer 128 includes a silicon-containing dielectricmaterial, such as SiN, SiCN, SiOC, or SiOCN. The first, second, andthird dielectric layers 126, 128, 129 may be formed by any suitabledeposition process, such as an ALD process or any conformal depositionprocess.

The first dielectric feature 130 may be formed by sequentiallydepositing the first and second dielectric layers 126, 128 on theexposed surfaces of the semiconductor device structure 100 and in thetrenches 114 a, 114 b, 114 c, 114 d and over the fin structures 112 a,112 b, 112 c. The third dielectric layer 119 is then formed on thesecond dielectric layer 128. The third dielectric layer 119 deposits inthe trench 114 b at a faster rate than the trenches 114 a, 114 c, 114 ddue to the small distance D2. Therefore, the third dielectric feature119 may completely fill the trench 114 b before the trenches 114 a, 114c, 114 d are filled with the third dielectric layer 119. Next, thefirst, second, and third dielectric layer 126, 128, 119 are recessedusing any suitable removal process, such as dry etch, wet, etch, or acombination thereof. The removal process may be selective etch processesthat remove portions of the first, second, and third dielectric layer126, 128, 119 but not the mask structure 110, the sacrificial layers107, the first semiconductor layers 106, and the second semiconductorlayers 108. Because the trenches 114 a, 114 c, 114 d are not completelyfilled and has a larger dimension (i.e., first distance D1) in the Ydirection compared to that of the trench 114 b (FIG. 2 ), the etchantremoves more of the first, second, and third dielectric layer 126, 128,119 in the trenches 114 a, 114 c, 114 d than the first, second, andthird dielectric layer 126, 128, 119 in the trench 114 b. As a result,the first, second, and third dielectric layer 126, 128, 119 in thetrenches 114 a, 114 c, 114 d are etched at a faster rate than the etchrate of the first, second, and third dielectric layer 126, 128, 119 inthe trench 114 b. The removal process is performed until the first,second, and third dielectric layer 126, 128, 119 in the trenches 114 a,114 c, 114 d are completely etched away. As a result of the removalprocess, the first, second, and third dielectric layer 126, 128, 119 onexposed surfaces of the semiconductor device structure 100 are removedexcept for the first, second, and third dielectric layer 126, 128, 119filled in the trench 114 b, as shown in FIGS. 4A and 4B. While notshown, the top of the first dielectric feature 130 may have a concaveprofile due to etching effects from the removal process on the first,second, and third dielectric layer 126, 128, 119.

In cases where the first dielectric feature 130 includes the firstdielectric layer 126, the first dielectric layer 126 may have athickness T1 ranging from 0.5 nm to about 5 nm. The second dielectriclayer 128 may be formed with a thickness T2 greater, equal, or less thanthe thickness T1 of the first dielectric layer 126. In some embodiments,the second thickness T2 is greater than the thickness T1 and may be in arange from 1 nm to about 10 nm. As will be discussed in more detailbelow with respect to FIG. 21 , exposed portions of the first dielectriclayer 126 not in contact with the first semiconductor layers 106 areremoved to allow a subsequent gate electrode layer to extend towards thesecond dielectric layer 128, which provides greater surface coveragearound the first semiconductor layers 106 for a better electricalcontrol over the nanosheet channels. If the thickness of the firstdielectric layer 126 is less than about 0.5 nm, the extension of thegate electrode layer 182 might not be sufficient to provide desiredelectrical control over the nanosheet channels. On the other hand, ifthe thickness of the first dielectric layer 126 is greater than about 5nm, the thickness of the second and third dielectric layers 128, 119 canbe reduced and the manufacturing cost is increased without significantadvantage.

In FIGS. 5A-5C, portions of the first, second, and third dielectriclayer 126, 128, 119 are recessed by a removal process. The recess of thefirst, second, and third dielectric layer 126, 128, 119 may be performedby any suitable process, such as dry etch, wet etch, or a combinationthereof. The removal process may be a selective process so that portionsof the first, second, and third dielectric layer 126, 128, 119 areremoved and the mask structures 110 and the sacrificial layers 107 arenot substantially affected. The recess process may be controlled so thatthe tops of the first, second, and third dielectric layer 126, 128, 119are substantially at a level below a top surface of the sacrificiallayers 107 but above a top surface of the topmost first semiconductorlayer 106 a in the stack of semiconductor layers 104. After the removalprocess, recesses 131 are formed above the first, second, and thirddielectric layer 126, 128, 119 and between the adjacent fin structures112 b, 112 c.

In FIGS. 6A-6C, a first high-k dielectric layer 140 is formed in eachrecess 131 (FIGS. 5A and 5B) formed as a result of removal of theportions of the first, second, and third dielectric layer 126, 128, 119.The first high-k dielectric layer 140 may be initially formed in therecess 131, the trenches 114 a, 114 c, 114 d, and over the maskstructure 110. Due to the small distance D2 (FIG. 2 ), the first high-kdielectric layer 140 fully fills the recesses 131 at a faster rate thanthat in the trenches 114 a, 114 c, 114 d. Next, the first high-kdielectric layer 140 are etched back using any suitable removal process,such as dry etch, wet, etch, or a combination thereof. Because thetrenches 114 a, 114 c, 114 d are not completely filled and has a largerdimension (i.e., first distance D1) in the Y direction compared to thatof the recess 131, the etchant removes the first high-k dielectric layer140 in the trenches 114 a, 114 c, 114 d at a faster rate than the firsthigh-k dielectric layer 140 in the recesses 131. The removal process isperformed until the high-k dielectric in the trenches 114 a, 114 c, 114d are completely etched away, as shown in FIGS. 6A and 6B.

The dielectric layer 140 may include a material having a k value greaterthan that of silicon oxide. In some embodiments, the first high-kdielectric layer 140 includes a material having a k value greater than7. Suitable materials for the first high-k dielectric layer 140 mayinclude, but are not limited to, SiN, SiON, SiCN, SiOCN, AlSi_(x)O_(y),Al₂O₃, or the like. Other suitable high-k materials, such as hafniumoxide (HfO₂), hafnium silicate (HfSiO), hafnium silicon oxynitride(HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide(HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HMO),hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), zirconium oxide(ZrO), zirconium silicon oxide (ZrSiO), titanium oxide (TiO), tantalumoxide (Ta₂O₅), yttrium oxide (Y₂O₃), may also be used. The first high-kdielectric layer 140 may be formed by any suitable process, such as aCVD, PECVD, FCVD, or ALD process. The first high-k dielectric layer 140may have a height along the Z direction ranging from about 10 nm toabout 30 nm.

In FIGS. 7A-7C, a resist layer 141 is formed on the exposed surfaces ofthe semiconductor device structure 100. The resist layer 141 may be anysuitable masking material, such as a photoresist layer, a BARC (bottomanti-reflective coating) layer, a SOG (spin-on-glass) layer, or a SOC(spin-on-carbon) layer, and may be deposited by spin coating or anysuitable deposition technique. The resist layer 141 is patterned toexpose certain regions of the semiconductor device structure 100, suchas regions that has an end cut 145. The end cut 145 is formed byremoving a portion of the fin structure (e.g., fin structure 112 b shownin FIG. 7C) so that the remaining fin structure 112 b is segmented. Thesegmentation isolates some of the transistors from another. The end cut145 may be performed by protecting portions of the fin structures by theresist layer 141. The exposed portions of fin structure not covered bythe resist layer 141 are removed in one or more etch processes. In oneembodiment shown in FIG. 7B, the etch processes remove the fin structure112 b (e.g., the stack of semiconductor layers 104 and the well portion116) to expose the sidewalls of the first high-k dielectric layer 140and the first dielectric layer 126. The etch processes are performeduntil the top portion of the substrate 101 is exposed. In oneembodiment, the top portion of the substrate 101 is removed so that anexposed top surface 115 of the substrate 101 is at a level below orslightly below an interface 117 between the first dielectric layer 126and the substrate 101.

In FIGS. 8A-8C, after formation of the end cut 145 in the fin structure112 b, the resist layer 141 is removed using any suitable removalprocess, such as ashing, dry etch, wet etch, or a combination thereof.Then, an insulating material 118 is formed on the substrate 101. Theinsulating material 118 fills the trenches 114 a, 114 c, 114 d, and theend cut 145 between neighboring fin structures 112 until the finstructures 112 are embedded in the insulating material 118. Then, aplanarization operation, such as a chemical mechanical polishing (CMP)method and/or an etch-back method, is performed to remove the insulatingmaterial 118 and the mask structures 110 until the top of the finstructures 112 is exposed. Next, the insulating material 118 is recessedto form an isolation region (or shallow trench isolation (STI) region)120. The recess of the insulating material 118 exposes portions of thefin structures 112, such as the stack of semiconductor layers 104. Insome embodiments where the first dielectric layer 126 and the insulatingmaterial 118 are formed of the same material, a portion of the firstdielectric layer 126 is also removed during the recess of the insulatingmaterial 118. As a result, sidewalls of the second dielectric layer 128and the first high-k dielectric layer 140 are exposed. A top surface ofthe insulating material 118 may be level with or slightly below asurface defined between the second semiconductor layer 108 b and thewell portion 116 formed from the substrate 101. The insulating material118 may be made of silicon oxide, silicon nitride, silicon oxynitride(SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-kdielectric material, or any suitable dielectric material. The insulatingmaterial 118 may be formed by any suitable method, such as low-pressurechemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) orflowable CVD (FCVD).

In FIGS. 9A-9C, a cladding layer 132 is formed on the sidewalls of thestack of semiconductor layers 104. The cladding layer 132 may be formedon the exposed surfaces of the stack of semiconductor layers 104, thesacrificial layer 107, the first high-k dielectric layer 140, and theisolation region 120. The cladding layer 132 also forms on the sidewallsof the second dielectric layer 128 and the first high-k dielectric layer140. The cladding layer 132 may be formed by a conformal process, suchas an ALD process. Next, portions of the cladding layer 132 are removedby an anisotropic etch process so that the cladding layer 132 onhorizontal surfaces of the fin structures 112 a, 112 b, 112 c (e.g., topsurfaces of the sacrificial layer 107), the first high-k dielectriclayer 140, and the insulating material 118 is removed. The removalprocess does not remove the cladding layer 132 formed on the verticalsurfaces (e.g., the sidewalls) of the fin structures 112 a, 112 b, 112c, the second dielectric layer 128, and the first high-k dielectriclayer 140. The cladding layer 132 may have a thickness ranging fromabout 2 nm to about 20 nm, for example about 5 nm to about 13 nm. Insome embodiments, the cladding layer 132 includes a semiconductormaterial. In some embodiments, the cladding layer 132 and the secondsemiconductor layers 108 are made of the same material having the sameetch selectivity. For example, the cladding layer 132 and the secondsemiconductor layers 108 include SiGe. The cladding layer 132 and thesecond semiconductor layer 108 may be removed subsequently to createspace for the gate electrode layer.

In FIGS. 10A-10C, a second dielectric feature 134 is formed in thetrenches 114 a, 114 c, 114 d (FIGS. 9A and 9B) and the region above theend cut 145 (FIG. 9B). The second dielectric feature 134 includes afourth dielectric layer 136 and a fifth dielectric layer 138 formed onthe fourth dielectric layer 136. The fourth dielectric layer 136 mayinclude the same material and have substantially the same thickness asthe second dielectric layer 128. The fifth dielectric layer 138 mayinclude the same material as the third dielectric layer 119. The fourthdielectric layer 136 may be formed on the isolation region 120, thecladding layer 132, the sacrificial layer 107, and the first high-kdielectric layer 140, by a conformal process, such as an ALD process.The fifth dielectric layer 138 is then formed on the fourth dielectriclayer 136 in the trenches 114 a, 114 c, 114 d, and over the finstructures 112 a, 112 b, 112 c and the first dielectric feature 130, bya flowable process, such as an FCVD process. Next, a planarizationprocess, such as a CMP process, is performed until the sacrificial layer107 is exposed.

In FIGS. 11A-11C, portions of the second dielectric feature 134 areremoved using any suitable etch-back process, such as a dry etch, wetetch, or a combination thereof. The etch-back process may be one or moreselective etch processes that remove the fourth and fifth dielectriclayers 136, 138 but not the cladding layers 132, the sacrificial layers107, and the first high-k dielectric layer 140. The etch-back process isperformed so that the tops of the fourth and fifth dielectric layers136, 138 are at substantially the same level as the tops of the firstdielectric feature 130. The etch-back process forms a recess above thefourth and fifth dielectric layers 136, 138 and between the adjacentcladding layers 132. Next, a second high-k dielectric layer 143 isformed in each recess formed as a result of removal of the portions ofthe fourth and fifth dielectric layers 136, 138. Portions of the secondhigh-k dielectric layer 143 formed over the sacrificial layers 107, thecladding layers 132, and the first high-k dielectric layer 140 are thenremoved by a planarization process so that the top surfaces of thesacrificial layers 107, the cladding layers 132, and the first high-kdielectric layer 140 are substantially co-planar with the top surfacesof the second high-k dielectric layer 143. The second high-k dielectriclayer 143 may include or be formed of the same material as the firsthigh-k dielectric layer 140. The first high-k dielectric layer 140 andthe first dielectric feature 130 together may be referred to as a firstdielectric structure 147. Likewise, the second high-k dielectric layer143 and the second dielectric feature 134 together may be referred to asa second dielectric structure 149.

In FIGS. 12A-12C, the sacrificial layers 107 and portions of thecladding layers 132 are removed. The removal of the sacrificial layers107 and the recess of the cladding layers 132 may be performed by anysuitable etch-back process, such as dry etch, wet etch, or a combinationthereof. The etch process may be controlled so that the remainingcladding layers 132 are substantially at the same level as the topsurface of the topmost first semiconductor layer 106 a in the stack ofsemiconductor layers 104. The top of the cladding layer 132 above theend cuts 145 and between the first and second dielectric structures 147,149 may be at a level higher than the tops of the remaining claddinglayers 132 due to the narrower spacing. In cases where the claddinglayers 132 and the sacrificial layers 107 are made of SiGe, theetch-back process may be a selective etch process that removes thecladding layers 132 and the sacrificial layers 107, but does not removethe layers of the first and second dielectric structures 147, 149. Theremoval of the sacrificial layers 107 and the cladding layer 132 exposesthe top surfaces of the fin structures 112 a, 112 b, 112 c, and aportion of the first and fourth dielectric layers 126, 136.

FIG. 13 is a perspective view of one of various stages of manufacturingthe semiconductor device structure 100, in accordance with someembodiments. FIGS. 14D-19D are top views of the semiconductor devicestructure 100 of FIG. 13 , which may represent a portion of the layoutof fin structures in the SRAM cell 103. FIGS. 14A-19A arecross-sectional side views of various stages of manufacturing thesemiconductor device structure 100 taken along line A-A of FIG. 14D andline A-A of FIG. 13 , in accordance with some embodiments. FIGS. 14B-19Bare cross-sectional side views of various stages of manufacturing thesemiconductor device structure 100 taken along line B-B of FIG. 14D, inaccordance with some embodiments. FIGS. 14C-19C are cross-sectional sideviews of various stages of manufacturing the semiconductor devicestructure 100 taken along line C-C of FIG. 13 .

As shown in FIGS. 13 and 14A, one or more sacrificial gate stacks 142are formed on the semiconductor device structure 100. The sacrificialgate stacks 142 may each include a sacrificial gate dielectric layer144, a sacrificial gate electrode layer 146, and a mask structure 148.The sacrificial gate dielectric layer 144 may include one or more layersof dielectric material, such as SiO₂, SiN, a high-k dielectric material,and/or other suitable dielectric material. In some embodiments, thesacrificial gate dielectric layer 144 may be deposited by a CVD process,a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, aPVD process, or other suitable process. The sacrificial gate electrodelayer 146 may include polycrystalline silicon (polysilicon). The maskstructure 148 may include an oxygen-containing layer 150 and anitrogen-containing layer 152. The sacrificial gate electrode layer 146and the mask structure 148 may be formed by various processes such aslayer deposition, for example, CVD (including both LPCVD and PECVD),PVD, ALD, thermal oxidation, e-beam evaporation, or other suitabledeposition techniques, or combinations thereof.

The sacrificial gate stacks 142 may be formed by first depositingblanket layers of the sacrificial gate dielectric layer 144, thesacrificial gate electrode layer 146, and the mask structure 148,followed by pattern and etch processes. By patterning the sacrificialgate stack 142, the stacks of semiconductor layers 104 of the fins 112a, 112 b, 112 c are partially exposed on opposite sides of thesacrificial gate stack 142. While two sacrificial gate stacks 142 areshown, the number of the sacrificial gate stacks 142 is not limited totwo. More than two sacrificial gate stacks 142 may be arranged along theX direction in some embodiments. Next, a spacer 154 is formed onsidewalls of the sacrificial gate stacks 142, as shown in FIGS. 13, 14C,and 14D. The spacer 154 may be formed by first depositing a conformallayer (e.g., by an ALD process) that is subsequently etched back (e.g.,by RIE) to form sidewall spacers 154. During the anisotropic etchprocess, most of the spacer 154 is removed from horizontal surfaces,such as the tops of the fin structures 112 a, 112 b, 112 c, the claddinglayers 132, the first and second dielectric structures 147, 149, leavingthe spacers 154 on the vertical surfaces, such as the sidewalls ofsacrificial gate stacks 142. The spacer 154 may be made of a dielectricmaterial such as silicon oxide, silicon nitride, silicon carbide,silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinationsthereof.

In FIGS. 15A-15D, exposed portions of the fin structures 112, exposedportions of the cladding layers 132, and exposed portions of the firstand second dielectric structures 147, 149 not covered by the sacrificialgate stacks 142 and the spacers 154 are selectively recessed by usingone or more suitable etch processes, such as dry etch, wet etch, or acombination thereof. In some embodiments, exposed portions of the stacksof semiconductor layers 104 of the fin structures 112 are removed,exposing portions of the well portions 116, as shown in FIG. 15B. Insome embodiments, the exposed portions of the fin structures 112 arerecessed to a level at or slightly below the top surface of theinsulating material 118.

In FIGS. 16A-16D, edge portions of each second semiconductor layer 108(e.g., 108 a, 108 b) of the stack of semiconductor layers 104 areremoved horizontally along the X direction. The removal of the edgeportions of the second semiconductor layers 108 forms cavities. In someembodiments, the portions of the second semiconductor layers 108 areremoved by a selective wet etching process. In cases where the secondsemiconductor layers 108 are made of SiGe and the first semiconductorlayers 106 are made of silicon, the second semiconductor layer 108 canbe selectively etched using a wet etchant such as, but not limited to,ammonium hydroxide (NH₄OH), tetramethylammonium hydroxide (TMAH),ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH)solutions.

After removing edge portions of each second semiconductor layers 108, adielectric layer is deposited in the cavities to form dielectric spacers151. The dielectric spacers 151 may be made of a low-K dielectricmaterial, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectricspacers 151 may be formed by first forming a conformal dielectric layerusing a conformal deposition process, such as ALD, followed by ananisotropic etching to remove portions of the conformal dielectric layerother than the dielectric spacers 151. The dielectric spacers 151 areprotected by the first semiconductor layers 106 during the anisotropicetching process. The remaining second semiconductor layers 108 (e.g.,108 a, 108 b) are capped between the dielectric spacers 151 along the Xdirection.

In FIGS. 17A-17D, epitaxial S/D features 160 are formed on the wellportions 116 of the fin structures 112 a, 112 b, 112 c. The epitaxialS/D features 160 may be the S/D regions. For example, one of a pair ofepitaxial S/D features 160 located on one side of the stack ofsemiconductor layers 104 can be a source region, and the other of thepair of epitaxial S/D features 160 located on the other side of thestack of semiconductor layers 104 can be a drain region. A pair ofepitaxial S/D features 160 includes a source epitaxial feature 160 and adrain epitaxial feature 160 connected by the nanosheet channels (i.e.,the first semiconductor layers 106). In this disclosure, a source and adrain are interchangeably used, and the structures thereof aresubstantially the same.

For n-channel FETs, the epitaxial S/D features 160 may include one ormore layers of Si, SiP, SiC, SiCP, or a group III-V material (InP, GaAs,AlAs, InAs, InAlAs, InGaAs). In some embodiments, the epitaxial S/Dfeatures 160 may be doped with n-type dopants, such as phosphorus (P),arsenic (As), etc, for n-type devices. For p-channel FETs, the epitaxialS/D features 160 may include one or more layers of Si, SiGe, SiGeB, Ge,or a group III-V material (InSb, GaSb, InGaSb). In some embodiments, theepitaxial S/D features 160 may be doped with p-type dopants, such asboron (B). The epitaxial S/D features 160 may grow both vertically andhorizontally to form facets, which may correspond to crystalline planesof the material used for the substrate 101. The epitaxial S/D features160 may be formed by an epitaxial growth method using CVD, ALD or MBE.

After the formation of the epitaxial S/D features 160, the first andsecond high-k dielectric layers 140, 143 are removed to reduce theoverall k value of the semiconductor device structure 100. The first andsecond high-k dielectric layers 140, 143 may be removed using anysuitable removal process, such as dry etch, wet etch, or a combinationthereof. The removal process may be a selective etch process thatremoves the first and second high-k dielectric layers 140, 143 but notthe first, second, fourth dielectric layer 126, 128, 136, the insulatingmaterial 118, and the well portion 116 of the substrate 101. The removalof the first and second high-k dielectric layers 140, 143 exposes thetops of the second, third, fourth, and fifth dielectric layers 128, 119,136, 138.

In FIGS. 18A-18D, a contact etch stop layer (CESL) 162 is formed on theepitaxial S/D features 160, the tops of the second, third, fourth, andfifth dielectric layers 128, 119, 136, 138, and the nitrogen-containinglayer 152 of the mask structure 148. The CESL 162 is also formed on aportion of the insulating material 118 and the first dielectric layer126 adjacent the end cuts 145. The CESL 162 may include anoxygen-containing material or a nitrogen-containing material, such assilicon nitride, silicon carbon nitride, silicon oxynitride, carbonnitride, silicon oxide, silicon carbon oxide, or the like, or acombination thereof. The CESL 162 may be formed by CVD, PECVD, ALD, orany suitable deposition technique. In some embodiments, the CESL 162 isa conformal layer formed by the ALD process. Next, an interlayerdielectric (ILD) layer 164 is formed on the CESL 162. The materials forthe ILD layer 164 may include an oxide formed fromtetraethylorthosilicate (TEOS), un-doped silicate glass, or dopedsilicon oxide such as borophosphosilicate glass (BPSG), fused silicaglass (FSG), phosphosilicate glass (PSG), boron doped silicon glass(BSG), and/or other suitable dielectric materials. The ILD layer 164 maybe deposited by a PECVD process or other suitable deposition technique.In some embodiments, after formation of the ILD layer 164, thesemiconductor device structure 100 may be subject to a thermal processto anneal the ILD layer 164.

In FIGS. 19A-19D, a planarization process, such as a CMP process, isperformed until the tops of the sacrificial gate electrode layer 146 andthe spacers 154 are exposed. The planarization process removes portionsof the ILD layer 164 and the CESL 162 disposed on the sacrificial gatestacks 142. In some embodiments, the ILD layer 164 may be recessed to alevel at the top of the sacrificial gate electrode layer 146. In suchcases, a nitrogen-containing layer (not shown), such as a SiCN layer,may be formed on the recessed ILD layer 164 to protect the ILD layer 164during subsequent etch processes.

FIGS. 20-25 are cross-sectional views of various stages of manufacturingthe semiconductor device structure 100 of FIG. 19A in accordance withsome embodiments. In FIG. 20 , the sacrificial gate electrode layer 146(FIGS. 19A and 19C) and the sacrificial gate dielectric layer 144 (FIGS.19A and 19C) are removed, exposing the top surfaces of the claddinglayers 132 and the stacks of semiconductor layers 104 (e.g., topmostfirst semiconductor layer 106 a). The sacrificial gate electrode layer146 may be first removed by any suitable process, such as dry etch, wetetch, or a combination thereof, followed by the removal of thesacrificial gate dielectric layer 144, which may be performed by anysuitable process, such as dry etch, wet etch, or a combination thereof.In some embodiments, a wet etchant such as a tetramethylammoniumhydroxide (TMAH) solution can be used to selectively remove thesacrificial gate electrode layer 146 but not the spacers 154, the firstand second dielectric structures 147, 149, the CESL 162, and the ILDlayer 164.

Next, the cladding layers 132 and the second semiconductor layers 108are removed. The removal process exposes portions of the first andsecond dielectric structures 147, 149 (e.g., the first and fourthdielectric layers 126, 136, and first and second high-k dielectriclayers 140, 143), the first semiconductor layers 106, and a portion ofthe insulating material 118. The removal process may be any suitableprocesses, such as dry etch, wet etch, or a combination thereof. Theremoval process may be a selective etch process that removes thecladding layers 132 and the second semiconductor layers 108 but not thefirst semiconductor layers 106, the spacers 154, the first dielectricfeatures 130, the second dielectric features 134, and the CESL 162. Incases where the cladding layers 132 and the second semiconductor layers108 are made of SiGe, and the first semiconductor layers 106 are made ofsilicon, a selective wet etching including an ammonia and hydrogenperoxide mixtures (APM) may be used. As a result of the etch process,openings 166 are formed, leaving the first semiconductor layers 106(e.g., first semiconductor layers 106 a, 106 b) protruded from opposingsides of the first dielectric feature 130. Specifically, each of thefirst semiconductor layers 106 a, 106 b has a first end in contact withthe first dielectric layer 126 and a second end (i.e., distal end)extending away from the first end, as shown in FIG. 20 . Having thefirst end of the first semiconductor layers 106 a, 106 b directlyconnected to a portion of the first dielectric feature 130 saves thespace for subsequent metal gate and increases the overall patterndensity. The portions of the first semiconductor layers 106 not coveredby the dielectric spacers 151 are exposed in the openings 166. Eachfirst semiconductor layer 106 serves as a nanosheet channel of thenanosheet transistor/fork-like gate nanosheet transistor.

Upon removal of the cladding layers 132 and the second semiconductorlayers 108, an end cap region 181 is formed between distal ends of thefirst semiconductor layers 106 (e.g., first semiconductor layers 106 a,106 b) and sidewalls of the second dielectric features 134. In someembodiments, the end cap region 181 has a distance D3 along the Ydirection ranging between about 2 nm to about 15 nm. That is, the seconddielectric structure 149 is spaced apart from the distal ends of thefirst semiconductor layers 106 by the distance D3. The distance D3 isvariable depending on the thickness of the cladding layer 132. If thespacing D3 is less than 2 nm, the subsequent IL 178 and HK dielectriclayer 180 (FIG. 22 ) may immaturely block the end cap regions 181 atdistal ends of the topmost first semiconductor layer 106 a, which inturn prevents the subsequent layers (e.g., gate electrode layer 182)from getting in and forming around the first semiconductor layers 106 a,106 b.

In FIG. 21 , after the removal of the cladding layers 132 and the secondsemiconductor layers 108, portions of the first dielectric layer 126 areremoved by a removal process. The removal process is a controlledisotropic process so that exposed portions of the first dielectric layer126 (e.g., portions of the first dielectric layer 126 exposed to theopening 166) are removed, while the first dielectric layer 126 betweenthe second dielectric layer 128 and the first semiconductor layers 106a, 106 b remains substantially intact. That is, portions of the firstdielectric layer 126 not in contact with the first semiconductor layers106 a, 106 b are entirely removed by the removal process. The removalprocess may be a selective etch process that removes the firstdielectric layer 126 but not the first semiconductor layers 106 a, 106,the spacers 154, second dielectric layer 128 and the fourth dielectriclayer 136, and the CESL 162. The removal of the exposed first dielectriclayer 126 increases the surface coverage of the gate electrode layer 182(FIG. 22 ) around at least three surfaces of the first semiconductorlayers 106 a, 106 b. Particularly, the removal of the exposed firstdielectric layer 126 allows the gate electrode layer 182 to extendtowards the second dielectric layer 128 and over a plane defined by aninterface 174 between the first dielectric layer 126 and the firstsemiconductor layers 106 a, 106 b. Since the gate electrode layer 182provides greater surface coverage around the first semiconductor layer106 a, 106 b, a better electrical control over the nanosheet channels(e.g., first semiconductor layers 106 a, 106 b) is achieved and thusleakage in the off state is reduced.

In FIG. 22 , an interfacial layer (IL) 178 is formed to surround atleast three surfaces (except for the surfaces being in contact with thefirst dielectric layer 126 and with the epitaxial S/D features 160) ofthe first semiconductor layers 106 (e.g., first semiconductor layers 106a, 106 b). The IL 178 may also form on the exposed first dielectriclayer 126 (e.g., first dielectric layer 126 disposed between the seconddielectric layer 128 and the first semiconductor layers 106 a, 106 b)and the exposed surfaces of the well portion 116 of the substrate 101.In some embodiments, the IL 178 may form on the first semiconductorlayers 106 but not on the exposed first dielectric layer 126. The IL 178may include or be made of an oxygen-containing material or asilicon-containing material, such as silicon oxide, silicon oxynitride,oxynitride, hafnium silicate, etc. The IL 178 may be formed by CVD, ALDor any suitable conformal deposition technique. In one embodiment, theIL 178 is formed using ALD. The thickness of the IL 178 is chosen basedon device performance considerations. In some embodiments, the IL 178has a thickness ranging from about 0.5 nm to about 2 nm.

Next, a high-k (HK) dielectric layer 180 is formed on the exposedsurfaces of the semiconductor device structure 100. In some embodiments,the HK dielectric layer 180 is formed on the IL 178, a portion of theinsulating material 118, and on the exposed surfaces of the first andsecond dielectric structures 147, 149 (e.g., the second dielectriclayers 128, the fourth dielectric layers 136, the first and secondhigh-k dielectric layers 140, 143), as shown in FIG. 22 . The HKdielectric layer 180 may include or be made of the same material as thefirst and second high-k dielectric layers 140, 143. The HK dielectriclayer 180 may be a conformal layer formed by a conformal process, suchas an ALD process or a CVD process. The HK dielectric layer 180 may havea thickness of about 0.5 nm to about 3 nm, which may vary depending onthe application.

After formation of the IL 178 and the HK dielectric layer 180, a gateelectrode layer 182 is formed in the openings 166 (FIG. 21 ). The gateelectrode layer 182 is formed on the HK dielectric layer 180 to surrounda portion of each first semiconductor layer 106 a, 106 b and on the HKdielectric layer 180 that is in contact with the first and seconddielectric structures 147, 149 and the insulating material 118. The gateelectrode layer 182 may include one or more layers of conductivematerial, such as polysilicon, aluminum, copper, titanium, tantalum,tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobaltsilicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, othersuitable materials, and/or combinations thereof. The gate electrodelayer 182 may be formed by PVD, CVD, ALD, electro-plating, or othersuitable method. The gate electrode layer 182 is formed to apredetermined height above the first and second dielectric structures147, 149, as shown in FIG. 22 .

In FIG. 23 , one or more metal gate etching back (MGEB) processes areperformed so that the gate electrode layer 182 is recessed to the samelevel as the top surfaces of the first and second dielectric features130, 134. The MGEB processes may be any suitable process, such as a dryetch, a wet etch, or a combination thereof. In some embodiments, theMGEB processes include a selective dry etch process that removes thegate electrode layer 182 but does not substantially affect the HKdielectric layer 180, the spacer 154 (FIG. 19C), and the CESL 162 (FIG.19C), and the ILD layer 164. In some embodiments, portions of thespacers 154 may be etched back so that the top surface of the spacers154 is higher than the top surfaces of the gate electrode layer 182 andthe HK dielectric layer 180. In such cases, trenches formed above thegate electrode layer 182 as a result of the MGEB processes may be filledwith a self-aligned contact (SAC) layer. The SAC layer can be formed ofany dielectric material that has different etch selectivity than theCESL 162 and serves as an etch stop layer during subsequent trench andvia patterning for metal contacts.

After the MGEB processes, the first and second high-k dielectric layers140, 143, as well as a portion of the HK dielectric layer 180 formedthereon are removed. The removal process may be any suitable process,such as dry etch, wet etch, or a combination thereof. In someembodiments, the removal process is a selective etch process thatremoves the first and second high-k dielectric layers 140, 143, and theHK dielectric layer 180 but not the gate electrode layer 182. Theremoval process is performed until the top surfaces of the first andsecond dielectric features 130, 134 are exposed. The top surfaces of thegate electrode layer 182, the HK dielectric layer 180, and the first andsecond dielectric features 130, 134 are substantially co-planar afterthe removal process. After removal of the first and second high-kdielectric layers 140, 143, adjacent gate electrode layers 182 areseparated, or cut-off, by the first and second dielectric features 130,134, as shown in FIG. 23 .

In FIG. 24 , a mask 184 is formed on the exposed surfaces of the gateelectrode layer 182, the first and second dielectric features 130, 134,the ILD layers 164 (FIG. 19C), the CESLs 162 (FIG. 19C), the spacers 154(FIG. 19C), and the HK dielectric layers 180. The mask 184 may includeor made of a semiconductor material, such as amorphous silicon,polysilicon, or the like, and may be formed by any suitable depositiontechnique, such as CVD, PECVD, MOCVD, FCVD, or MBE. In one embodiment,the mask 184 includes amorphous silicon. Next, an opening is formed inthe mask 184 and a first dielectric material 188 is formed in theopening and on the mask 184. The opening exposes portions of the topsurfaces of the first dielectric feature 130 (e.g., the top surfaces ofthe first and second dielectric layers 126, 128) and may be formed by aphotolithography process and one or more etch processes. The firstdielectric material 188 is in contact with (and coplanar with) topsurfaces of at least the second dielectric layer 128 and the thirddielectric layer 119. The first dielectric material 188 may include orbe formed of a nitrogen-containing layer, such as a nitride. In someembodiments, the first dielectric material 188 includes SiN. The firstdielectric material 188 formed over the mask 184 may be removed byusing, for example, CMP, until a top surface of the mask 184 is exposed.While not shown, two or more openings may be formed in the mask 184 toexpose top surfaces of the first dielectric features 130 disposed inother regions.

In FIG. 25 , the mask 184 is removed and a conductive layer 190 isformed in the region where the mask 184 was removed. The mask 184 may beremoved using any suitable process, such as a dry etch, a wet etch, or acombination thereof. In some embodiments, the removal process is aselective etch process that removes the mask 184 but does not remove thefirst dielectric material 188, the gate electrode layer 182, the firstdielectric features 130, the second dielectric features 134, the ILDlayers 164 (FIG. 19C), the CESLs 162 (FIG. 19C), the spacers 154 (FIG.19C), and the HK dielectric layers 180. The conductive layer 190 mayinclude or be made of a material having one or more of W, Ru, Mo, Co,Ni, Ti, Ta, Cu, Al, TiN and TaN, and may be formed by any suitableprocess, such as PVD, ECP, or CVD. A planarization process may then beperformed until the first dielectric material 188 is exposed.

Next, a second dielectric material 192 is formed on the conductive layer190 and the first dielectric material 188 until a desired thickness isreached. The second dielectric material 192 may include or be formed ofthe same material as the first dielectric material 188. In someembodiments, the second dielectric material 192 includes a nitride, suchas SiN. The first dielectric material 188 and the second dielectricmaterial 192 function as a self-aligned dielectric structure 195, asshown in FIG. 25 . The conductive layer 190 may provide a signal, suchas an electrical current, to the gate electrode layer 182 locatedtherebelow. In the embodiment shown in FIG. 25 , the signal can beprovided to adjacent gate electrode layers 182 (e.g., gate electrodelayers 182 a, 182 b) via the conductive layer 190. In such a case, asingle signal sent to the gate electrode layer 182 a or gate electrodelayer 182 b may control both nanosheet channel regions. Meanwhile, theself-aligned dielectric structure 195 cuts off the conductive layers 190(i.e., conductive layers 190 a, 190 b are isolated from each other bythe self-aligned dielectric structure 195). Since the first dielectricfeature 130 also isolates the gate electrode layer 182 b from the gateelectrode layer 182 c, a signal (e.g., an electrical current) sent tothe conductive layer 190 a and the gate electrode layers 182 a, 182 b incontact with the conductive layer 190 a is not provided to or sharedwith the conductive layer 190 b and the gate electrode layer 182 c onthe other side of the self-aligned dielectric structure 195.

It has been observed that when end cuts are made in fin structuresbefore formation of a dielectric wall, the dielectric wall may be formedin a discontinuous manner and materials of sacrificial gate stacks(e.g., sacrificial gate dielectric layer and sacrificial gate electrodelayer) may not properly deposit on the exposed surfaces of thesemiconductor device structure due to discontinuity of the dielectricwall. As a result, small gaps or voids can be formed at regions betweenthe sacrificial gate stacks and the discontinuous dielectric feature.When removing the cladding layers and second semiconductor layers toexpose nanosheet channel, these small gaps or voids may trap portions ofsemiconductive materials (e.g., cladding layers 132 and secondsemiconductor layers 108) and become a defect source for electricalshorts. In contrast to the approach of making end cuts in the finstructures before formation of the dielectric wall, the embodiment shownin FIG. 25 proposes forming a continuous dielectric wall (e.g., firstdielectric feature 130) before end cuts in the fin structures. The firstdielectric feature 130 extends all the way down to the well portions 116of the substrate 101. The first dielectric feature 130 forms onedielectric wall that isolates adjacent active fin structures (e.g., finstructures 112 b, 112 c), which are to be formed as a forksheettransistor in a SRAM cell. For other active fin structures (e.g., finstructures 112 a, 112 b), the second dielectric feature 134 is used toisolate upper part (e.g., the first semiconductor layers 106 a, 106 b)of the fin structures 112 a and 112 b, and the insulating material 118(e.g., STI region) is used to isolate lower part (e.g., well portion 116of the substrate 101) of the fin structures 112 a and 112 b. Therefore,the dielectric wall extends continuously between two fin structures foreffective isolation of transistors, such as two adjacent pull-uptransistors in the SRAM cell. Since the dielectric wall is formed beforemaking end cuts on the fin structures, any defect sources for electricalshorts as discussed above are eliminated.

FIG. 26 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure 100 of FIG. 19C, inaccordance with some embodiments. In FIG. 26 , S/D contacts 193 areformed through the ILD layer 164 (FIG. 19C) and the CESL 162 (FIG. 19C)to be in contact with the epitaxial S/D features 160 via a silicidelayer 139. The S/D contacts 193 may be made of a material including oneor more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN and TaN, any suitablemetal material, and can be formed by CVD, ALD, electro-plating, or othersuitable deposition technique. The silicide layers 139 may be made of ametal or metal alloy silicide, and the metal includes a noble metal, arefractory metal, a rare earth metal, alloys thereof, or combinationsthereof. For n-channel FETs, the silicide layers 139 may be made of amaterial including one or more of TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi,ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, or combinationsthereof. For p-channel FETs, the silicide layers 139 may be made of amaterial including one or more of NiSi, CoSi, MnSi, Wsi, FeSi, RhSi,PdSi, RuSi, PtSi, IrSi, OsSi, or combinations thereof. Once the S/Dcontracts 193 are formed, a planarization process, such as CMP, isperformed to expose the top surface of the second dielectric material192 (or the top surface of the SAC layer if used).

FIG. 27 is a perspective view of one of the various stages ofmanufacturing the semiconductor device structure 100, in accordance withsome embodiments. FIG. 27 shows the first semiconductor layers 106(e.g., first semiconductor layers 106 a, 106 b) are in contact with atleast the fourth dielectric layer 136, the fifth dielectric layer 138,the CESL 162, and the ILD layer 164 due to removal of the fin structures112 (e.g., fin structure 112 b) to form end cuts 145. In the embodimentshown in FIG. 27 , the CESL 162 is in contact with the first dielectriclayer 126, the second dielectric layer 128, the insulating material 118,the fourth dielectric layer 136, the fifth dielectric layer 138, the ILDlayer 164, the spacer 154, and the first semiconductor layers 106 (e.g.,first semiconductor layers 106 a, 106 b).

FIG. 28 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure 100, in accordance withsome embodiments. FIG. 28 illustrates a portion of the semiconductordevice structure 100 showing the structural relationship between thefirst semiconductor layers 106 and various layers exposed thereto or incontact with. Dotted lines denote the first semiconductor layers 106 a,106 b hidden from view. As can be seen in the embodiment shown in FIGS.27 and 28 , at least portions of the nanosheet channels (e.g., firstsemiconductor layers 106 a, 106 b) extending from one side of the firstdielectric feature 130 (e.g., the second dielectric layer 128) are incontact with four different dielectric layers, that is, the CESL 162,the ILD layer 164, the fourth dielectric layer 136, and the fifthdielectric layer 138. In addition, at least portions of the nanosheetchannels (e.g., first semiconductor layers 106 a, 106 b) extending fromopposing side of the first dielectric feature 130 are in contact withthe epitaxial S/D features 160.

FIGS. 29-50 show exemplary sequential processes for manufacturing asemiconductor device structure 200, in accordance with some alternativeembodiments. It is understood that additional operations can be providedbefore, during, and after processes shown by FIGS. 29-50 , and some ofthe operations described below can be replaced or eliminated, foradditional embodiments of the method. The order of theoperations/processes may be interchangeable. FIG. 29 is a perspectiveview of one of various stages of manufacturing the semiconductor devicestructure 200, in accordance with some embodiments. FIG. 29 illustratesa state of the semiconductor device structure 200 after the stack ofsemiconductor layers 104, the sacrificial layer 107, and the maskstructure 110 are formed on the substrate 101 and patterned to form finstructures 112 a, 112 b, 112 c. Next, an insulating material 218, suchas the insulating material 118, is formed in the trenches 114 a, 114 b,114 c, 114 d (FIG. 2 ) and over the fin structures 112 a, 112 b, 112 c.A planarization process is then performed on the semiconductor devicestructure 200 to expose the tops of the fin structures 112 a, 112 b, 112c.

FIGS. 30C-38C are top views of the semiconductor device structure 200 ofFIG. 29 , which may represent a portion of the layout of active finstructures in a SRAM cell 203, such as the SRAM cell 103. In oneembodiment shown in FIGS. 30C-38C, the fin structures 112 b and 112 ccan be used to form pull-up (PU) transistors and the fin structure 112 acan be used to form pull-down (PD) transistor or pass-gate (PG)transistor in a 6T SRAM cell. FIGS. 30A-38A are cross-sectional sideviews of various stages of manufacturing the semiconductor devicestructure 200 taken along line A-A of FIG. 30C, in accordance with someembodiments. FIGS. 30B-38B are cross-sectional side views of variousstages of manufacturing the semiconductor device structure 200 takenalong line B-B of FIG. 30C, in accordance with some embodiments.

In FIGS. 30A-30C, a resist layer 241, such as the resist layer 141, isformed on the exposed surfaces of the semiconductor device structure200. The resist layer 241 is patterned to expose certain regions of thesemiconductor device structure 200, such as regions that require an endcut 245. Like the end cut 145, the end cut 245 is formed by removing aportion of the fin structure (e.g., fin structure 112 b) to isolate someof the transistors from another. The exposed portion of fin structurenot covered by the resist layer 241 is removed in one or more etchprocesses. The etch processes remove the fin structure 112 b (e.g., thestack of semiconductor layers 104 and the well portion 116) to expose atop portion of the substrate 101. In one embodiment shown in FIG. 30 ,the top portion of the substrate 101 is removed so that an exposed topsurface 215 of the substrate 101 is at a level below or slightly belowan interface 217 between the insulating material 118 and the substrate101. The removal of the fin structure 112 b forms a trench 211 at theend cut 245. The trench 211 exposes the insulating material 218 and thetop surface 215 of the substrate 101.

In FIGS. 31A-31C, after formation of the end cut 245 in the finstructure 112 b, the resist layer 241 is removed using any suitableremoval process, such as ashing, dry etch, wet etch, or a combinationthereof. Then, a dielectric fin 213 is formed in the trench 211 (FIG.30B) and over the insulating material 218 and the mask structure 110.The dielectric fin 213 is in contact with the top surface 215 of thesubstrate 101 and the insulating material 218. The dielectric fin 213may be formed of any suitable dielectric material that has differentetch selectivity than the insulating material 218. In one embodiment,the dielectric fin 213 includes or is made of the same material as thesecond dielectric layer 128 and can be formed by the same depositionprocess as discussed above. Next, a planarization process, such as aCMP, is performed on the semiconductor device structure 200 until theinsulating material 218 is exposed. The dielectric fin 213 is thenetched back so that the top of the dielectric fin 213 is at about thesame height as the sacrificial layer 107. The dielectric fin 213 has aheight H1 in a range of about 20 nm to about 300 nm, which may varydepending on the original height of the fin structures 112. Theetch-back process may be any suitable process, such as dry etch, wetetch, or a combination thereof. In one embodiment, the etch-back is aselective etch process that removes the dielectric fin 213 but not theinsulating material 218.

In FIGS. 32A-32C, the mask structure 110 is removed and the insulatingmaterial 218 is recessed to form an isolation region (or shallow trenchisolation (STI) region) 220. The recess of the insulating material 218exposes portions of the dielectric fin 213 and the fin structures 112,such as sidewalls of the stack of semiconductor layers 104. A topsurface of the insulating material 218 may be level with or slightlybelow a surface defined between the second semiconductor layer 108 b andthe well portion 116 formed from the substrate 101. The mask structure110 and portions of the insulating material 218 may be removed using anysuitable process, such as dry etch, wet etch, or a combination thereof.The trenches 114 a, 114 b, 114 c, 114 d, and a recess 221 (formedbetween the fin structure 112 c and the dielectric fin 213) are revealedafter the recess of the insulating material 218.

In FIGS. 33A-33C, a first dielectric layer 226, a second dielectriclayer 228, and a third dielectric layer 219 are formed on the exposedsurfaces of the semiconductor device structure 200. In one embodiment,the first, second, and third dielectric layers 226, 228, 219 are formedin the trenches 114 a, 114 b, 114 c, 114 d, and recess 221, and over thedielectric fin 213 and the fin structures 112 a, 112 b, 112 c. The firstdielectric layer 226 may include or be formed of the same material asthe first dielectric layer 126. The second dielectric layer 228 mayinclude or be formed of the same material as the second dielectric layer128. The third dielectric layer 219 may include or be formed of the samematerial as the third dielectric layer 119. The first, second, and thirddielectric layers 226, 228, 219 may be formed by an ALD process or anyconformal deposition process. In some embodiments, the first dielectriclayer 226 is optional and may be omitted. In the embodiment shown inFIGS. 33A and 33B, the first dielectric layer 226 is in contact with atleast the insulating material 218, the stack of semiconductor layers 104(e.g., first semiconductor layers 106 a-b and second semiconductorlayers 108 a-b), the sacrificial layer 107, and the dielectric fin 213.The second and third dielectric layers 228, 219 are then sequentiallyformed on the first dielectric layer 226. The third dielectric layer 219deposits in the trench 114 b and recess 221 (FIGS. 32A and 32B) at afaster rate than the trenches 114 a, 114 c, 114 d due to the smalldistance D2 (FIG. 2 ). Therefore, the third dielectric layer 219 maycompletely fill the trench 114 b and recess 221 before the trenches 114a, 114 c, 114 d are filled with the third dielectric layer 219.

The first, second, and third dielectric layers 226, 228, 219 may havethe same thickness as the first, second, and third dielectric layers126, 128, 129. Likewise, exposed portions of the first dielectric layer226 not in contact with the first semiconductor layers 106 aresubsequently removed to allow a subsequent gate electrode layer toextend towards the second dielectric layer 228, which provides greatersurface coverage around the first semiconductor layers 106 for a betterelectrical control over the nanosheet channels.

In FIGS. 34A-34C, the first, second, and third dielectric layer 226,228, 219 are recessed using any suitable removal process, such as dryetch, wet, etch, or a combination thereof. The removal process may beselective etch processes that remove portions of the first, second, andthird dielectric layer 226, 228, 219 but not the sacrificial layers 107,the first and second semiconductor layers 106, 108, the insulatingmaterial 218, and the dielectric fin 213. Because the trenches 114 a,114 c, 114 d are not completely filled and has a larger dimension (i.e.,first distance D1, FIG. 2 ) in the Y direction compared to that of thetrench 114 b and recess 221 (FIGS. 32A and 32B), the first, second, andthird dielectric layer 226, 228, 219 in the trenches 114 a, 114 c, 114 dare etched at a faster rate than the etch rate of the first, second, andthird dielectric layer 226, 228, 219 in the trench 114 b and recess 221.The removal process is performed until the first, second, and thirddielectric layer 226, 228, 219 in the trenches 114 a, 114 c, 114 d arecompletely etched away. The first, second, and third dielectric layer226, 228, 219 in the trench 114 b (FIG. 32A) and recess 221 (FIG. 32B)are referred to as a first dielectric feature 230. The first dielectricfeature 230 and the insulating material 218 isolates two adjacent finstructures (e.g., fin structures 112 b, 112 c).

In FIGS. 35A-35C, a cladding layer 232, such as the cladding layer 132,is formed on the sidewalls of the stack of semiconductor layers 104, theexposed surfaces of the dielectric fin 213, the sacrificial layer 107,and portions of the insulating material 218. The cladding layer 132 maybe formed using the same method of forming the cladding layer 232. Thecladding layer 232 may have the same thickness as the cladding layer132.

In FIGS. 36A-36C, a second dielectric feature 234, such as the seconddielectric feature 134, is formed in the trenches 114 a, 114 c, 114 d(FIGS. 35A and 35B). The second dielectric feature 234 includes a fourthdielectric layer 236 and a fifth dielectric layer 238 formed on thefourth dielectric layer 236. The fourth dielectric layer 236 may includethe same material as the fourth dielectric layer 136. The fifthdielectric layer 238 may include the same material as the fifthdielectric layer 138. The fourth dielectric layer 236 may be formed onportions of the insulating material 218, the cladding layer 232, thedielectric fin 213, the top of the first dielectric feature 230, and thesacrificial layer 107 by a conformal process, such as an ALD process.The fifth dielectric layer 238 is then formed on the fourth dielectriclayer 236 in the trenches 114 a, 114 c, 114 d, and over the finstructures 112 a, 112 b, 112 c, the dielectric fin 213, the top of thefirst dielectric feature 230 and the sacrificial layer 107, by aflowable process, such as an FCVD process. Next, a planarizationprocess, such as a CMP process, is performed until the sacrificial layer107 is exposed.

The fourth dielectric layer 236 may have substantially the samethickness as the fourth dielectric layer 136, such as about 1 nm toabout 12 nm. As will be discussed below with respect to FIG. 46 , an endcap region 281 is formed between distal ends of the first semiconductorlayers 106 and the fourth dielectric layer 236 after removal of thecladding layers 232. Thus, if the thickness of the fourth dielectriclayer 136 is greater than 12 nm, the end cap region 281 may becomenarrow so that subsequent layers (e.g., IL 278 and HK dielectric layer280) may immaturely block the end cap region 281 and prevent thesubsequent layers (e.g., gate electrode layer 282) from getting in andforming around the first semiconductor layers 106. On the other hand, ifthe thickness of the fourth dielectric layer 236 is less than 1 nm, itmay not provide enough protection for the fifth dielectric layer 238during various etch processes and therefore, the purpose of the seconddielectric feature 234 is compromised.

In FIGS. 37A-37C, portions of the second dielectric feature 234 areremoved using the same removal process as those used to remove thesecond dielectric feature 134 discussed above. The removal process isperformed so that the tops of the fourth and fifth dielectric layers136, 138 are at or slightly above the top surface of the topmost firstsemiconductor layer 106 a. Next, a high-k dielectric layer 243, such asthe second high-k dielectric layer 143, is formed in each recess formedas a result of removal of the portions of the fourth and fifthdielectric layers 136, 138. The high-k dielectric layer 243 may beformed by the same method for forming the second high-k dielectric layer143. The high-k dielectric layer 243 and the first dielectric feature230 together may be referred to as a first dielectric structure 247.Likewise, the high-k dielectric layer 243 and the second dielectricfeature 234 together may be referred to as a second dielectric structure249.

In FIGS. 38A-38C, the sacrificial layers 107 and portions of thecladding layers 232 are removed. The removal process may be the same asthe etch-back process used for removing the cladding layers 132discussed above, and can be controlled so that the remaining claddinglayers 232 are at the same level as the top surface of the topmost firstsemiconductor layer 106 a in the stack of semiconductor layers 104. Thetop of the cladding layer 232 above the end cut 245 and between thedielectric fin 213 and the second dielectric structure 249 may be at alevel higher than the tops of the remaining cladding layers 232 due tothe narrower spacing. The removal of the sacrificial layers 107 and thecladding layer 232 exposes the top surfaces of the fin structures 112 a,112 b, 112 c, portions of the first and fourth dielectric layers 226,236, and the dielectric fin 213.

FIG. 39 is a perspective view of one of various stages of manufacturingthe semiconductor device structure 200, in accordance with someembodiments. FIGS. 40D-45D are top views of the semiconductor devicestructure 200 of FIG. 39 , which may represent a portion of the layoutof fin structures in the SRAM cell 203. FIGS. 40A-45A arecross-sectional side views of various stages of manufacturing thesemiconductor device structure 200 taken along line A-A of FIG. 40D andline A-A of FIG. 39 , in accordance with some embodiments. FIGS. 40B-45Bare cross-sectional side views of various stages of manufacturing thesemiconductor device structure 200 taken along line B-B of FIG. 40D, inaccordance with some embodiments. FIGS. 40C-45C are cross-sectional sideviews of various stages of manufacturing the semiconductor devicestructure 200 taken along line C-C of FIG. 39 .

As shown in FIGS. 39 and 40A, one or more sacrificial gate stacks 142,as shown and discussed above with respect to FIG. 13 , are formed on thesemiconductor device structure 200. The one or more sacrificial gatestacks 142 may be formed using the same processes as those discussedabove with respect to FIG. 13 .

In FIGS. 41A-41D, exposed portions of the fin structures 112, exposedportions of the cladding layers 232, and exposed portions of the firstand second dielectric structures 247, 249 not covered by the sacrificialgate stacks 142 and the spacers 154 are selectively recessed by usingone or more suitable etch processes, in a similar fashion as thosediscussed above with respect to FIGS. 15A-15D. In some embodiments,portions of the stacks of semiconductor layers 104 of the fin structures112 are removed to expose portions of the well portions 116, as shown inFIG. 41B. In some embodiments, the etchant used for removal of thestacks of the semiconductor layers 104 and the cladding layers 232 mayalso remove a portion of the dielectric fin 213. Therefore, thedielectric fin 213 is recessed to have a height H2 that is shorter thanthe height H1 (FIG. 31B). The etchant may etch the stacks ofsemiconductor layers 104/cladding layers 232 and the dielectric fin 213at a rate of about 2:1 (stacks of semiconductor layers 104/claddinglayers 232:dielectric fin 213). In some embodiments, the dielectric fin213 is recessed so that a top surface 223 of the dielectric fin 213 isat or below the top of the first and second dielectric structures 247,249. In some embodiments, the dielectric fin 213 is recessed so that atop surface 223 of the dielectric fin 213 is at or below the top of thefirst and second dielectric features 230, 234. In some embodiments, thedielectric fin 213 is recessed so that a top surface 223 of thedielectric fin 213 is at a level about 40% to about 75% height of thefirst and second dielectric features 230, 234, for example about 50%height of the first and second dielectric features 230, 234.

In FIGS. 42A-42D, edge portions of each second semiconductor layer 108(e.g., 108 a, 108 b) of the stack of semiconductor layers 104 areremoved and replaced with the dielectric spacers 151. The remainingsecond semiconductor layers 108 (e.g., 108 a, 108 b) are capped betweenthe dielectric spacers 151 along the X direction. The dielectric spacers151 may be formed in a similar fashion as those discussed above withrespect to FIGS. 16A-16D.

In FIGS. 43A-43D, the epitaxial S/D features 160 are formed on the wellportions 116 of the fin structures 112 a, 112 b, 112 c. The epitaxialS/D features 160 may be formed in a similar fashion as those discussedabove with respect to FIGS. 17A-17D. After the formation of theepitaxial S/D features 160, the high-k dielectric layers 243 are removedto reduce the overall K value of the semiconductor device structure 200.The removal of the high-k dielectric layers 243 exposes the tops of thesecond, third, fourth, and fifth dielectric layers 228, 219, 236, 238.

In FIGS. 44A-44D, the CESL 162 is formed on the epitaxial S/D features160, the tops of the second, third, fourth, and fifth dielectric layers228, 219, 236, 238, and the nitrogen-containing layer 152 of the maskstructure 148. The CESL 162 is also formed on a portion of theinsulating material 218 and the first dielectric layer 226 adjacent theend cut 245. Next, the ILD layer 164 is formed on the CESL 162. The CESL162 and the ILD layer 164 may be formed in a similar fashion as thosediscussed above with respect to FIGS. 18A-18D.

In FIGS. 45A-45D, a planarization process, such as a CMP process, isperformed until the tops of the sacrificial gate electrode layer 146 andthe spacers 154 are exposed. As can be seen in FIG. 45B, the epitaxialS/D features 160 of adjacent fin structures 112 (e.g., fin structures112 a and 112 c) are isolated from each other by at least the dielectricfin 213 extending upwardly from the substrate 101 and the ILD layer 164,as well as the first and second dielectric features 230, 234, and theinsulating material 218 and the ILD layer 164 extending below and aboveof the first and second dielectric features 230, 234.

FIGS. 46-48 are cross-sectional views of one of various stages ofmanufacturing the semiconductor device structure 200 of FIG. 45A inaccordance with some embodiments. In FIG. 46 , the sacrificial gateelectrode layer 146 (FIGS. 45A and 45C), the sacrificial gate dielectriclayer 144 (FIGS. 45A and 45C), and the cladding layers 232 are removed,exposing the top surfaces of the cladding layers 232 and the stacks ofsemiconductor layers 104 (e.g., topmost first semiconductor layer 106a). The sacrificial gate electrode layer 146, the sacrificial gatedielectric layer 144, and the cladding layers 232 are removed in asimilar fashion as those discussed above with respect to FIG. 20 .Openings 266 are formed as a result of removal of the sacrificial gateelectrode layer 146, the sacrificial gate dielectric layer 144, and thecladding layers 232, leaving the first semiconductor layers 106 (e.g.,first semiconductor layers 106 a, 106 b) protruded from opposing sidesof the first dielectric feature 230. Specifically, each of the firstsemiconductor layers 106 a, 106 b has a first end in contact with thefirst dielectric layer 226 and a second end (i.e., distal end) extendingaway from the first end, as shown in FIG. 46 . The portions of the firstsemiconductor layers 106 not covered by the dielectric spacers 151 areexposed in the openings 266. Each first semiconductor layer 106 a, 106 bserves as a nanosheet channel of the nanosheet transistor/fork-like gatenanosheet transistor.

Likewise, upon removal of the cladding layers 232 and the secondsemiconductor layers 108, an end cap region 281 is formed between distalends of the first semiconductor layers 106 (e.g., first semiconductorlayers 106 a, 106 b) and sidewalls of the second dielectric features234. In some embodiments, the end cap region 281 has a distance D4 alongthe Y direction ranging between about 2 nm to about 15 nm. The distanceD4 is variable depending on the thickness of the fourth dielectric layer236. If the spacing D4 is less than 2 nm, the subsequent IL 178 and HKdielectric layer 180 (FIG. 47 ) may immaturely block the end cap regions281 at distal ends of the topmost first semiconductor layer 106 a, whichin turn prevents the subsequent layers (e.g., gate electrode layer 182)from getting in and forming around the first semiconductor layers 106 a,106 b.

Next, exposed portions of the first dielectric layer 226 are removed bya removal process, such as a controlled isotropic process as thosediscussed above with respect to FIG. 21 . The first dielectric layer 226between the second dielectric layer 228 and the first semiconductorlayers 106 a, 106 b remains substantially intact. Likewise, the removalof the exposed first dielectric layer 226 allows the subsequent gateelectrode layer 182 to extend towards the second dielectric layer 228and over a plane defined by an interface 274 between the firstdielectric layer 226 and the first semiconductor layers 106 a, 106 b,thereby providing a better electrical control over the nanosheetchannels (e.g., first semiconductor layers 106 a, 106 b).

In FIG. 47 , the IL 178 is formed to surround at least three surfaces(except for the surface being in contact with the first dielectric layer226) of the first semiconductor layers 106 (e.g., first semiconductorlayers 106 a, 106 b). The IL 178 may also form on the exposed surfacesof the first dielectric layer 226 (e.g., first dielectric layer 126disposed between the second dielectric layer 228 and the firstsemiconductor layers 106 a, 106 b) and the exposed surfaces of the wellportion 116 of the substrate 101. The HK dielectric layer 180 is thenformed on the IL 178, a portion of the insulating material 218, and onthe exposed surfaces of the first and second dielectric features 230,234 (e.g., the second dielectric layers 228, the fourth dielectriclayers 236). Then, the gate electrode layer 182 is formed in theopenings 266 (FIG. 46 ). The IL 178, the HK dielectric layer 180, andthe gate electrode layer 182 may be formed in a similar fashion as thosediscussed above with respect to FIG. 22 .

One or more metal gate etching back (MGEB) processes are then performed,in a similar fashion as those discussed above with respect to FIG. 23 ,so that the gate electrode layer 182 is recessed to the same level asthe top surfaces of the first and second dielectric features 230, 234.After the MGEB processes, the high-k dielectric layers 243 and a portionof the HK dielectric layer 180 formed thereon are removed. The topsurfaces of the gate electrode layer 182, the HK dielectric layer 180,and the first and second dielectric features 230, 234 are substantiallyco-planar after the removal process. After removal of the high-kdielectric layers 243, adjacent gate electrode layers 182 are separated,or cut-off, by the first and second dielectric features 230, 234, asshown in FIG. 47 .

In FIG. 48 , the conductive layer 190 and the self-aligned dielectricstructure 195 are formed on the exposed surfaces of the gate electrodelayer 182, the first and second dielectric features 230, 234, the ILDlayers 164 (FIG. 45C), the CESLs 162 (FIG. 45C), the spacers 154 (FIG.45C), and the HK dielectric layers 180. The conductive layer 190includes conductive layers 190 a, 190 b which are isolated from eachother by the self-aligned dielectric structure 195. The conductive layer190 and the self-aligned dielectric structure 195 may be formed in asimilar fashion as those discussed above with respect to FIGS. 24 and 25. The conductive layer 190 may provide a signal, such as an electricalcurrent, to the gate electrode layer 182 located therebelow.

In the embodiment shown in FIG. 48 , a signal, such as an electricalcurrent, can be provided to adjacent gate electrode layers 182 (e.g.,gate electrode layers 182 a, 182 b) via the conductive layer 190. Insuch a case, a single signal sent to the gate electrode layer 182 a orgate electrode layer 182 b may control both nanosheet channel regions.Since the first dielectric feature 230 also isolates the gate electrodelayer 182 b from the gate electrode layer 182 c, a signal sent to theconductive layer 190 a and the gate electrode layers 182 a, 182 b incontact with the conductive layer 190 a is not provided to or sharedwith the conductive layer 190 b and the gate electrode layer 182 c onthe other side of the self-aligned dielectric structure 195.

As can be seen in FIG. 48 , the dielectric structure 195, and theproposed first dielectric feature 230 extending all the way to the wellportions 116 of the substrate 101 forms a continuous dielectric wallthat can effectively isolate two immediately adjacent fin structures 112(e.g., fin structures 112 b, 112 c). In addition, the upper parts (e.g.,the first semiconductor layers 106 a, 106 b) of the fin structures 112 aand 112 b are isolated by the second dielectric feature 234, while thelower part (e.g., well portion 116 of the substrate 101) of the finstructures 112 a and 112 b are isolated by the insulating material 218(e.g., STI region). The use of the proposed first dielectric feature230, the second dielectric feature 234, and the insulating material 218forms continuous dielectric wall between two adjacent fin structures 112and can eliminate any source for electrical shorts when comparing to theconventional device structure using the discontinuous dielectricfeature, as discussed above with respect to FIG. 25 ).

FIG. 49 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure 200 of FIG. 45C, inaccordance with some embodiments. In FIG. 49 , S/D contacts 193 areformed through the ILD layer 164 (FIG. 45C) and the CESL 162 (FIG. 45C)and in contact with the epitaxial S/D features 160 via a silicide layer139. The S/D contacts 193 and the silicide layer 139 may be formed in asimilar fashion as those discussed above with respect to FIG. 26 . Oncethe S/D contracts 193 are formed, a planarization process is performedto expose the top surface of the second dielectric material 192 (or thetop surface of the SAC layer if used).

FIG. 50 is a perspective view of one of various stages of manufacturingthe semiconductor device structure 200, in accordance with someembodiments. FIG. 50 shows that the dielectric fin 213 is provided atthe end cut 245 formed as a result of removal of the fin structure 112(e.g., fin structure 112 b in FIG. 29 ). The dielectric fin 213 isformed to have a height that is at a level between the two adjacentfirst semiconductor layers 106 a, 106 b. Therefore, upper portions ofthe first semiconductor layers 106 (e.g., first semiconductor layers 106a) are in contact with the ILD layer 164, while lower portions of thefirst semiconductor layers 106 (e.g., first semiconductor layers 106 b)are in contact with the dielectric fin 213.

FIG. 51 is a cross-sectional side view of one of various stages ofmanufacturing the semiconductor device structure 200, in accordance withsome embodiments. FIG. 51 illustrates a portion of the semiconductordevice structure 200 showing the structural relationship between thefirst semiconductor layers 106 (represented by dotted lines) and variouslayers exposed thereto or in contact with. In one embodiment shown inFIG. 51 , at least portions of the nanosheet channels (e.g., firstsemiconductor layer 106 a) extending from one side of the firstdielectric feature 230 are in contact with the ILD layer 164, at leastportions of the nanosheet channels (e.g., first semiconductor layer 106b) extending from one side of the first dielectric feature 230 are incontact with the dielectric fin 213. In other words, semiconductorlayers in the stack of semiconductor layers 104 are in contact withdifferent dielectric layers. In addition, at least portions of thenanosheet channels (e.g., first semiconductor layers 106 a, 106 b)extending from opposing side of the first dielectric feature 230 are incontact with the epitaxial S/D features 160.

It is understood that the semiconductor device structures 100, 200 mayundergo further complementary metal oxide semiconductor (CMOS) and/orback-end-of-line (BEOL) processes to form various features such astransistors, contacts/vias, interconnect metal layers, dielectriclayers, passivation layers, etc. The semiconductor device structures100, 200 may also include backside contacts (not shown) on the backsideof the substrate 101 by flipping over the semiconductor device structure100, removing the substrate 101, and selectively connecting source ordrain feature/terminal of the epitaxial S/D features 160 to a backsidepower rail (e.g., positive voltage VDD or negative voltage VSS) throughthe backside contacts. Depending on the application, the source or drainfeature/terminal of the epitaxial S/D features 160 and the gateelectrode layers 182 may be connected to a frontside power source.

Various embodiments described herein offer multiple advantages over thestate-of-art technology. According to embodiments of the presentdisclosure, at least one dielectric feature having a structure oflow-k/oxide/low-k is formed on a substrate and continuously extendedbetween two active fin structures before making end cuts on the finstructures. The dielectric feature can be one dielectric structurehaving its bottom in contact with the substrate. Alternatively, thedielectric feature can include an upper portion formed of the dielectricstructure and a lower portion formed of an insulating material (e.g.,STI region). Additionally or alternatively, the dielectric feature canbe formed by filling an end cut of active fin structures with adielectric fin. In any case, the dielectric feature avoids electricalshorts at transistors, such as two adjacent pull-up transistors in theSRAM cell. In addition, portions of a high-k dielectric layer on thedielectric feature are laterally recessed to allow a subsequent gateelectrode layer to form around the nanosheet channels with greatersurface coverage. As a result, a better electrical control over thenanosheet channels is achieved.

An embodiment is a method for forming a semiconductor device structure.The method includes forming first, second, and third fin structures froma substrate, wherein the first fin structure includes a first pluralityof semiconductor layers, the second fin structure includes a secondplurality of semiconductor layers, and the third fin structure includesa third plurality of semiconductor layers, and wherein each of thefirst, second, and third plurality of semiconductor layers comprisesfirst semiconductor layers and second semiconductor layers.

The method includes forming an insulating material between the first,second, and third fin structures, forming an end cut in the second finstructure, the end cut exposing an upper portion of the substrate,forming a dielectric fin in the end cut, forming a first dielectricfeature on the insulating material and between the first fin structureand the dielectric fin, forming a second dielectric feature on theinsulating material and between the dielectric fin structure and thethird fin structure, forming a sacrificial gate stack on a portion ofthe first fin structure, the second fin structure, the third finstructure, the first dielectric feature, and the second dielectricfeature, removing a portion of the first fin structure, the third finstructure, and the dielectric fin not covered by the sacrificial gatestack, removing the sacrificial gate stack to expose portions of thefirst, second, and third fin structures, removing the secondsemiconductor layers of the first, second, and third plurality ofsemiconductor layers. The method further includes forming a gateelectrode layer to surround at least three surfaces of the firstsemiconductor layers of the first, second, and third plurality ofsemiconductor layers.

Another embodiment is a method for forming a semiconductor devicestructure. The method includes forming a fin structure from a substrate,the fin structure comprising a plurality of first semiconductor layersand a plurality of second semiconductor layers alternatingly stacked,forming a dielectric fin over the substrate, the dielectric fin beingparallel to the fin structure, forming an insulating material betweenthe fin structure and the dielectric fin, recessing the insulatingmaterial to expose the plurality of the first and second semiconductorlayers and an upper portion of the dielectric fin, forming a dielectricfeature over the insulating material between the fin structure and thedielectric fin, forming a sacrificial gate stack on a portion of the finstructure and the dielectric feature, removing a portion of the finstructure and the dielectric fin not covered by the sacrificial gatestack, forming a source/drain (S/D) feature on the fin structure,forming a contact etch stop layer (CESL) on the S/D feature, thedielectric feature, and the dielectric fin, forming an interlayerdielectric (ILD) layer on the CESL, and removing the sacrificial gatestack and the second semiconductor layers.

A further embodiment is a method. The method includes forming a finstructure from a substrate, the fin structure comprising a plurality offirst semiconductor layers and a plurality of second semiconductorlayers alternatingly stacked, each first and second semiconductor layerextending along a first direction, forming a first dielectric feature onthe substrate, the first dielectric feature extending along a seconddirection perpendicular to the first direction, forming a seconddielectric feature over the substrate, the second dielectric featureextending along the section direction, forming a sacrificial gate stackon a portion of the fin structure and the first dielectric feature,removing the plurality of first and second semiconductor layers notcovered by the sacrificial gate stack to expose the substrate, forming asource/drain (S/D) feature on the exposed substrate, forming a contactetch stop layer (CESL) on exposed surfaces of the S/D feature and thefirst dielectric feature, forming an interlayer dielectric (ILD) layeron the CESL, removing the sacrificial gate stack and the secondsemiconductor layers, and forming a gate electrode layer to surround atleast three surfaces of each of the first semiconductor layers.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. A method for forming a semiconductor device structure, comprising:forming first, second, and third fin structures from a substrate,wherein the first fin structure includes a first plurality ofsemiconductor layers, the second fin structure includes a secondplurality of semiconductor layers, and the third fin structure includesa third plurality of semiconductor layers, and wherein each of thefirst, second, and third plurality of semiconductor layers comprisesfirst semiconductor layers and second semiconductor layers; forming aninsulating material between the first, second, and third fin structures;forming an end cut in the second fin structure, the end cut exposing anupper portion of the substrate; forming a dielectric fin in the end cut;forming a first dielectric feature on the insulating material andbetween the first fin structure and the dielectric fin; forming a seconddielectric feature on the insulating material and between the dielectricfin structure and the third fin structure; forming a sacrificial gatestack on a portion of the first fin structure, the second fin structure,the third fin structure, the first dielectric feature, and the seconddielectric feature; removing a portion of the first fin structure, thethird fin structure, and the dielectric fin not covered by thesacrificial gate stack; removing the sacrificial gate stack to exposeportions of the first, second, and third fin structures; removing thesecond semiconductor layers of the first, second, and third plurality ofsemiconductor layers; and forming a gate electrode layer to surround atleast three surfaces of the first semiconductor layers of the first,second, and third plurality of semiconductor layers.
 2. The method ofclaim 1, further comprising: after removing a portion of the first finstructure, the third fin structure, and the dielectric fin, forming asource/drain feature on the exposed portions of the first fin structureand the third fin structure not covered by the sacrificial gate stack.3. The method of claim 2, further comprising: forming an interlayerdielectric (ILD) layer over the first dielectric feature, the seconddielectric feature, the dielectric fin, and the source/drain feature, sothat at least portion of the first semiconductor layers of the secondplurality of semiconductor layers are in contact with the ILD layer, andat least portion of the first semiconductor layers of the secondplurality of semiconductor layers are in contact with the dielectricfin.
 4. The method of claim 1, wherein forming an end cut in the secondfin structure comprises removing the second fin structure until a top ofthe substrate is exposed.
 5. The method of claim 1, wherein the end cutis formed by removing a top portion of the substrate such that anexposed top of the substrate is at a level below or slightly below aninterface defined by the insulating material and the substrate.
 6. Themethod of claim 5, wherein removing a portion of the first finstructure, the third fin structure, and the dielectric fin not coveredby the sacrificial gate stack is performed such that a top surface ofthe dielectric fin is at or below a top of the first and seconddielectric features.
 7. A method for forming a semiconductor devicestructure, comprising: forming a fin structure from a substrate, the finstructure comprising a plurality of first semiconductor layers and aplurality of second semiconductor layers alternatingly stacked; forminga dielectric fin over the substrate, the dielectric fin being parallelto the fin structure; forming an insulating material between the finstructure and the dielectric fin; recessing the insulating material toexpose the plurality of the first and second semiconductor layers and anupper portion of the dielectric fin; forming a dielectric feature overthe insulating material between the fin structure and the dielectricfin; forming a sacrificial gate stack on a portion of the fin structureand the dielectric feature; removing a portion of the fin structure andthe dielectric fin not covered by the sacrificial gate stack; forming asource/drain (S/D) feature on the fin structure; forming a contact etchstop layer (CESL) on the S/D feature, the dielectric feature, and thedielectric fin; forming an interlayer dielectric (ILD) layer on theCESL; and removing the sacrificial gate stack and the secondsemiconductor layers.
 8. The method of claim 7, wherein removing aportion of the fin structure and the dielectric fin not covered by thesacrificial gate stack is performed such that a top surface of thedielectric fin is at a level below a top surface of a topmost firstsemiconductor layer.
 9. The method of claim 8, wherein the S/D featureis formed to have a contact surface covering each of the plurality ofthe first semiconductor layers.
 10. The method of claim 8, wherein thedielectric fin is formed to have a contact surface that is free fromcontacting the topmost first semiconductor layer.
 11. The method ofclaim 7, wherein the CESL over the dielectric fin is formed to have atop surface at a level below a top surface of a topmost firstsemiconductor layer.
 12. The method of claim 11, wherein the CESL isformed to have a portion in contact with the top surface and a sidewallof the dielectric fin.
 13. The method of claim 7, further comprising:forming a gate electrode layer to surround at least three surfaces ofeach of the first semiconductor layers.
 14. The method of claim 7,wherein forming a dielectric feature further comprises: forming a firstdielectric layer in contact with at least the insulating material, thefirst and second semiconductor layers, and the dielectric fin; forming asecond dielectric layer on the first dielectric layer; and forming athird dielectric layer on the second dielectric layer, wherein the firstand third dielectric layers comprise a material chemically differentthan the second dielectric layer.
 15. The method of claim 14, whereinthe first dielectric layer is in contact with the dielectric fin. 16.The method of claim 15, wherein the second dielectric layer is incontact with the CESL.
 17. A method for forming a semiconductor devicestructure, comprising: forming a fin structure from a substrate, the finstructure comprising a plurality of first semiconductor layers and aplurality of second semiconductor layers alternatingly stacked, eachfirst and second semiconductor layer extending along a first direction;forming a first dielectric feature on the substrate, the firstdielectric feature extending along a second direction perpendicular tothe first direction; forming a second dielectric feature over thesubstrate, the second dielectric feature extending along the sectiondirection; forming a sacrificial gate stack on a portion of the finstructure and the first dielectric feature; removing the plurality offirst and second semiconductor layers not covered by the sacrificialgate stack to expose the substrate; forming a source/drain (S/D) featureon the exposed substrate; forming a contact etch stop layer (CESL) onexposed surfaces of the S/D feature and the first dielectric feature;forming an interlayer dielectric (ILD) layer on the CESL; removing thesacrificial gate stack and the second semiconductor layers; and forminga gate electrode layer to surround at least three surfaces of each ofthe first semiconductor layers.
 18. The method of claim 17, wherein thefirst dielectric feature and the second dielectric feature are separatedfrom each other by the CESL and the ILD.
 19. The method of claim 18,wherein the second dielectric feature, the CESL, and the ILD are incontact with each of the first semiconductor layers.
 20. The method ofclaim 18, wherein the S/D feature is formed such that a sidewall of theS/D feature is in contact with the first dielectric feature.